1. Field of the Invention
The present invention relates to a nonvolatile semiconductor device having electric programming/erasing function, and in particular to the nonvolatile semiconductor device, in which discrimination of data information, being written with using injection of hot electron, is made by verifying voltage of a bit line, thereby achieving a high-speed programming/erasing operation.
2. Description of Prior Art
A flush memory, having superior portability and anti-shock property, can be subjected to electric bulk erasing, therefore the needs thereof is spreading out rapidly in recent years, in particular, as a file for personal digital assistances, such as, a mobile personal computer, a digital still camera, etc. For expansion of it on the markets, it is indispensable to have high-speed operation, but with low electric power.
For the purpose of obtaining the high-speed operation, parallel operation is needed, however for realizing the high-speed operation with low electric power, there is a necessity of suppressing the current amount to be as small as possible. An operating method for achieving this is already known as a programming method of utilizing Fowler-Nordheim (FN) type tunneling phenomenon therein.
The programming operation in accordance with this method will be explained by referring to cross section views of memory cells in FIGS. 12A and 12B. A reference numeral 11 in the figures indicates a control gate, 12 a floating gate, 13 a source, 14 a drain, 15 a well, and 16 a substrate, respectively. With this method, for example, the source 13 of a memory cell selected to program is turned to OPEN, while turning the control gate to 17V and the drain 14 to 0V, as shown in the FIG. 12A, so as to inject electron into the floating gate 12 with utilizing the FN type-tunneling phenomenon, thereby performing the programming of data. In this instance, for protecting the memory cell unselected to program from the FN type-tunneling phenomenon occurring therein, unselect voltage of programming, for example, voltage of 5V is applied to the drain 14, as shown in the FIG. 12B.
With this programming method of applying such the FN type-tunneling phenomenon therein, since almost no current flows into each of the memory cells when operating in the programming mode, the high-speed programming operation can be achieved by increasing the number of cells, each of which performs the parallel operation and the programming of data as well, at the same time.
However, since the operation, so-called verification must be done, necessarily after the program operation; i.e., for conduction the verification on the data programmed, the parallel operation is also needed for that verify operation, in order to achieve the high-speed program operation. For performing this verification, there are known methods of using, such as, a current sense amplifier and a voltage sense amplifier therein.
In the method of the current sense amplifier, voltage of 0V is applied to a source line SS of the memory cell, while voltage of 1V is applied to the bit lines BLL and BLR, as shown in FIG. 13A, for example. Further, with applying the verify voltage onto the word line WL, the current Im flowing into the memory cell M and the current Iref flowing into a dummy memory cell DM at that instance are sensed to be compared with to each other in a current sense circuit 19.
On the other hand, in the method of the voltage sense amplifier, with turning the source line SS of the memory cell down to 0V, an internal supply voltage VRPCL to 3V, and a control signal to voltage; i.e., 1V+ the threshold voltage of N type MOS transistors, respectively, voltage of 1V is applied onto the bit line BLL. After that, by turning a signal RPCL to 0V and further applying the verify voltage to the word line WL, the voltage change on the bit line BLL is detected by a voltage sense circuit 21. Namely, when the threshold voltage of the memory cell M is higher than the verify voltage and no current flows therein, the voltage applied onto the bit line BLL does not change, therefore it is decided that the programming is completed, while when the threshold voltage of the memory cell M is lower than the verify voltage and current flows therein, the voltage applied onto the bit line BLL does comes down to 0V, therefore it is decided that the programming is not completed yet.
In any one of the verify methods, though current flows in the memory cell, the current is cut off by turning voltage supply from the internal supply voltage RPCL; i.e., turning the signal RPCL to 0V, in accordance with the method of the voltage sense amplifier, it is possible to operate the memory cell with the low electric power. Accordingly, it can be said that the method of the voltage sense amplifier is advantageous or profitable for obtaining the high-speed through the parallel operation.
From the mentioned above, it has been considered that using the programming method of applying such the FN type-tunneling phenomenon is the best method for realizing the high-speed operation with the low electric power, while making the verification in accordance with the method of the voltage sense amplifier.
However, by the method of programming with applying such the FN type-tunneling phenomenon, it is possible to operate the device with the low electric power, but on the contrary to this, the operation is slow in the data programming, therefore, still there is a limit to achieve the high-speed, if applying the parallel operation thereto.
Then, there is proposed a new cell, being operable with a low electric power through an improvement of programming efficiency, as well as, being fast in the programming operation, by the present inventors, as is described in Japanese Patent Application No. Hei 11-200242 (1999), filed on Jul. 14, 1999.
An outline of the programming operation in this new memory cell will be explained briefly, by referring to FIGS. 14A and 14B. A reference numeral 10 in the figures depicts a third gate; i.e., an assist gate (AG), while 11 the control gate, 12 the floating gate, 13 the source, 14 the drain, 15 the well, 16 the substrate, respectively. This memory cell comprises the third assist gate 10, as shown in the figures, in addition to the structures of the conventional memory cell having the control gate 11 and the floating gate 12.
In the programming operation, as is shown in the FIG. 14A, the programming of data is performed by injecting hot electron generated in the channel area defined between the source 13 and the drain 14m, while turning the source 13 of the selected memory cell for programming to 0V, the assist gate 10 to 2V, the control gate 11 to 12V, the drain 14 to 5V, respectively.
In this instance, for prohibiting the hot electron from generating in the unselected memory cell for programming, the drain 14 is turned to 0V as shown in the FIG. 14B. Since this memory cell has the assist gate 10, as was mentioned previously, when programming, a large electric field is formed in a lower portion of a boundary between the floating gate 12 and the assist gate 10, being wide in the horizontal direction and the vertical direction. With this, an increase is obtained in the generation of the hot electron and the injection efficiency as well; therefore it is possible to achieve the high-speed programming, in spite of the channel current, which is smaller than that in the conventional memory cell. Further, more details thereof will be explained in later, by referring to FIGS. 18 to 21.
Accordingly, since it is possible to expect the further high-speed and low electric power operation, by using the memory cell having the superior injection efficiency as described in the Japanese Patent Application No. Hei 11-200242 (1999), and further by using the verify method of the voltage sense amplifier, then the present inventors made study on various methods, which will be effective for the verification. However, various problems occur in those methods. Further, the present inventors study the problems that will be mentioned below, first.
As was mentioned previously, 0V is applied to the drain of the selected memory cell for programming while 5V to the drain of the unselected memory cell for programming, in accordance with the programming method of applying the FN type-tunneling phenomenon of the conventional method. On the contrary to this, 5V must be applied to the drain of the selected memory cell for programming while 0V to the drain of the unselected memory cell for programming, in accordance with the programming method by means of the hot electron injection. Due to this, it is impossible to introduce the program/verify circuits as they are, which were applied in the programming method of the FN type-tunneling phenomenon. Next, this will be explained in brief.
By referring to FIGS. 15A and 15B, explanation will be given on an outline of the methods for programming and verifying operations with using the FN type-tunneling phenomenon, on which the present inventors studied. The FIG. 15A shows the circuit diagram of it, and FIG. 15B a flowchart thereof.
First, the programming of data is done. For example, a program select data of 0V or a program unselect data of 3.3V is inputted from an I/O line (I/OL) to a node SLL through a Y gate MOSFET 31 and a Y pre-gate MOSFET 32, so as to turn the supply voltages VSLP and VSLN of the sense amplifier 33 to 5V and 0V, respectively, thereby turning the selected node SLL for programming to 0V while the unselected node SLL for programming to 5V.
Next, the internal supply voltage VPCL is turned to 3.3V, and the signal PCL to 3.3V+ the threshold voltage of N type MOS transistors. Due to this operation, the selected bit line BLL for programming, the node SLL of which is turned to 0V, comes down to 0V, and the unselected bit line BLL for programming, the node SLL of which is turned to 5V, to 3.3V, respectively. Herein, further a signal TRL is turned up to 5V+ the threshold voltage of N type MOS transistors. Due to this operation, the selected bit line BLL for programming comes down to 0V, while the unselected bit line BLL for programming up to 5V. Under this condition, the word line WL is turned up to 17V at the same time when the source line SS of the memory cell M is tuned into OPEN state. With those operation mentioned above, the FN type-tunneling phenomenon occurs only within the selected cell(s) for programming, so as to program data therein.
Next, the verifying operation is performed. With turning the source line SS of the memory cell down to 0V, while turning the internal supply voltage VRPCL up to 3.3V and the signal RPCL to 1V+ the threshold voltage of N type MOS transistors, then 1V is applied to the bit line BLL of the memory cell.
After that, the verify voltage is applied to the word line WL while turning the signal RPCL to 0V at the same time. Due to this operation, the voltage on the bit line BLL is held at 1V if the threshold voltage of the memory cell is higher than the verify voltage and then no current flows therein, on the other hand, it comes down to 0V if the threshold voltage of the memory cell is lower than the verify voltage and current flows therein.
After that, the signal TRL is turned to 3.3V, and then the data on the bit lines BLL are transferred to the output nodes SLL of the sense amplifier 33. Next, with turning the supply voltage VSLP of the sense amplifier 33 up to 3.3V while the voltage VSLN thereof down to 0V, the data on the output nodes SLL of the sense amplifier 33 are amplified to 3.3V and 0V, respectively. Next, under this condition, it is verified that the programming is completed in all the memory cells M.
If all of the nodes SLL are 3.3V, the programming operation is finished. When any one of the nodes SLL is 0V, preparation is made for the programming operation of a second time. Namely, with turning the supply voltage VSLP of the sense amplifier 33 up to 5V while the voltage VSLN thereof down to 0V, the voltages at the output nodes of the above-mentioned sense amplifier 33 are further amplified from 3.3V and 0V to 5V and 0V, respectively.
Due to this operation, the voltage at the node SLL comes to 5V when the threshold voltage of the memory cell M is higher than the verify voltage and then the programming is fully done, and while the voltage at the node SLL comes to 0V when the threshold voltage of the memory cell M is lower than the verify voltage and the programming is done insufficiently.
At the end, if the signal TRL is turned to 7V under this condition, the unselected signal for programming, such as 5V, is applied onto the bit lines BLL of the memory cells, each of which is programmed up to a desired threshold value by the programming of the first time, but the selected signal for programming of 0V is applied onto the bit lines BLL of the memory cells, in each of which the programming is done insufficiently.
The mentioned above is an outline of the operations of programming and verification with using the FN type-tunneling phenomenon.
On a while, an example of a flowchart is shown in FIG. 16, for such the operations of programming and verification through the hot electron injection, as was proposed by the Japanese Patent Application No. Hei 11-200242 (1999).
In the operation of programming through the hot electron injection, 5V must be applied to the drain of the selected memory cell for programming, while 0V to that of the unselected memory cell for programming, as shown in the FIGS. 14A and 14B. Namely, since the voltages being applied to the bit lines in the programming operation are turned over or reversed, it is impossible to adapt the circuit operation shown in the FIG. 15A, as it is.
An object of the present invention, therefore, is to provide a nonvolatile semiconductor device, performing the programming operation through the hot electron injection, and being applicable with the verify method of the voltage sense amplifier as well, thereby enabling a high-speed operation with low electric power.
With the nonvolatile semiconductor device, according to the present invention, the data is programmed through the hot electron injection into the floating gate, and the device comprises a voltage sense circuit for detecting or determining the voltage which is applied to the bit line is changed or not, depending upon the threshold voltage of the memory cell, for the purpose of the verification of the data programmed.
In particular, with the nonvolatile semiconductor device, in which such the third assist gate is provided as described in the Japanese Patent Application No. Hei 11-200242 (1999), the method of the voltage sense amplified is applied, so as to use also the third gate effectively, when verifying the data programming condition after completion of the data programming operation through the hot electron injection into the floating gate, thereby performing the verification effectively and with certainty.
For example, when verifying the programming of data, a verify voltage is applied to the control gate in the upper portion of the floating gate, which is smaller than the voltage when programming, while applying the voltage larger than that to the third gate, thereby enabling the verification effectively and with certainty.
Also, according to a representative one of the embodiments according to the present invention, between the output node of the verify circuit constructed with the sense amplifier of a flip-flop type and the bit line of the memory cell, there are connected a MOSFET for connecting between them and a converter circuit formed with a plural number of MOSFETs for converting and transferring the data which is verified by means of the verify circuit to the bit line, so as to invert the data verified at least one time, for example, thereby enabling the continuous programming operation into the memory cells, with which the programming is not yet completed sufficiently.